Multi-Core Architecture Synthesis
This section describes how Technical Architectures are generated using the information from the Logical Architecture in AutoFOCUS. Therby a Pareto-frontier is generated, where each Pareto element is optimal to a certain criteria.
Currently three optimizaton criteria (each of them are minimized) are supported: Number of nodes, end-to-end latency and power consumption.
Right click on the project in the Model Navigator view, and select DSE. This adds the Design Space Exploration (DSE) item in the model navigator view.
An Design Space Exploration (DSE) item opens in the Navigator View, containing already the manual deployment (from above). As we can use
the DSE also for Scheduling Synthesis later on, the (Manual) Deployment is already there (if existing).
By double-clicking on the DSE in the Navigator a DSE Editor opens (see below). In addition to the Scheduling Synthesis
and Deployment Synthesis from the previous manual, we now have a technical architecture generation section (left section) as shown below
Generating technical architecture (left section)
Generation
Select the logical architecture (there can be more than one) for which you want to generate the technical architecture and hit
TA Generation Wizard.
Select the top-level logical component (AdaptiveCruiseControl in this case) that should be included in the generation of technical architecture. A Filter on the right hand side enables to
generate technical architecture of the immediate child components or all components in the tree.
Press the NEXT button for the next wizard page.
As a result, a technical architecture generation settings dialog box appears. The "Node Range" option limits the search space.
Within this search space two different solutions will be generated: the solution with the lowest end-to-end latency and the solution with the lowest number of nodes, whereby the solution with the smallest number of nodes is not allowed to exceed a certain deadline. (Note: if the deadline is chose to low, no solution might be found)
These platforms will have the processors operating at 100% frequency i.e. full clock utilization. If you want to generate an additional solution which is efficient towards its energy consumption,
check "Energy Efficient Architectures" before generating the architecture. This option uses the concept of DVFS (Voltage and frequency scaling), where
the voltage and frequency of a microprocessor can be automatically adjusted for the sake of power consumption minimization. With this option checked the optimization algorithm searches for a solution where the cpu frequency can be as minimal as possibly without exceeding the corresponding deadline. (Note: If the deadline is chose to low, no solution might be found.)
The "Timeout" option does limit the time which the SMT solver gets to find the best solution.
Note: Low timeout value leads to a faster calculation but may also lead to a less optimal result and vice versa. The optimal choice of the timeout value depends on the time the user is willing to wait and the structure/size of the logical architecture.
Once the technical architecture has been generated successfully, click NEXT button to see the deployment results. As you can notice, the energy efficient deployment have the processor
operating at a frequency less than 100%. To save all the deployment, click select all and then click Save selected elements. Finally, click Finish.
Once the platforms have been generated, you can move over to the Model Navigator view to the left. Go to the DSE Schedule result of each of the generated platform to see how the
scheduling of the tasks takes place. The is illustrated by the snapshot below.
Looking at the scheduling view of Energy Efficient Deployment, this option has the maximum latency since the processor is not operating at 100% frequency. In case of Smallest number of
nodes option, the tasks execute sequentially since the minimum number of cores is 1. The scheduling view of each of the generated platform is shown in the snapshots below.
1. Smallest E2E - latency 40
2. Smallest Nr of Nodes - latency 50
3. Energy Efficient - latency 67