PikeOS Platform Architecture (Modeling, Code Generation)

We introduce a new Platform Architecture for AutoFOCUS3, called PikeOS Platform Architecture. It supports hierarchical modeling of the hardware architecture; the new DSE Perspective; and Code/Config Generation for Sysgo PikeOS Hypervisor.
This article is divided in two parts. In the first part we introduce the modeling concept of this new Platform Architecture. Followed by the second part, which describes the code&config generation process for the PikeOS Hypervisor.

NOTE: We provide an example model that demonstrates the new Platform Architecture. Please go to File -> Open AF3 Example -> Load ACC PikeOS Example.


Modeling of hierarchical Platform Architectures

This section introduces the modeling concepts of PikeOS Platform Architecture.

Model Elements

The PikeOS Platform Architecture allows modeling of hierarchical platform architectures. We allow three hierarchical levels: Board Level, Core Level and Partition Level. You can open the level below by double-clicking (i.e.: double-click on a "Board" to get from the "Board Level" to the "Core Level"). In the following we describe the different levels together with model elements belonging to them.

Linking of GPIO Ports

To allow information from a GPIO Port on the Board Level to be accessible down to the Resource Partition Level it is necessary to link these Ports together. This can be done in the Annotation "GPIO Link" (cf. figure below). Here, the GPIs(GPOs) at the Resource Partition level are connected to the GPIs(GPOs) at the Core level, which in turn are connected to the GPIs(GPOs) at the Board level. These GPIO link annotations are important, for e.g., while tracing down the pin numbers defined at the Board level all the way down to the Resource Partition level. Please look at the PikeOS ACC Example for more information.


Generating code and configuration files (experimental)

To generate the code for the PikeOS Hypervisor it is first necessary to deploy the logical components onto Resource Partitions. Also the mapping of the logical ports to hardware ports (board level GPIOs) needs to be done. After that it is possible to right-click on the "Deployment" in Model Navigator view and then click "Run DeploymentGenerator". This will prompt the user to select the directory for saving the code. Two directories will be generated, named, app and int. The former directory includes the code for the PikeOS application project while the latter directory includes the code for PikeOS Integration Project.



Generating VMIT file

To generate the VMIT file, the user needs to open "schedule for Generated Deployment". The VMIT file can be generated by clicking on "Generate VMIT File" button. The user will again be prompted to select a directory for storing the VMIT file. Since, in the previous step, two directories are already generated (app and int), the user can choose to save the VMIT file directly under the int directory (VMIT is a part of PikeOS integration project). This is illustrated as follows.

Hardware board for testing the generated code

The generated code for PikeOS Platform Architecture has been successfully tested on the Freescale IMX6 Sabrelite board. The configurations for this board can be found here.